US 12,254,915 B1
Integrated circuit structure and method for forming and operating the same
Dai-Ying Lee, Hsinchu County (TW); Teng-Hao Yeh, Zhubei (TW); Wei-Chen Chen, Taoyuan (TW); Rachit Dobhal, New Taipei (TW); Zefu Zhao, Taipei (TW); and Chee-Wee Liu, Taipei (TW)
Assigned to MACRONIX INTERNATIONAL CO., LTD., Hsinchu (TW)
Filed by MACRONIX INTERNATIONAL CO., LTD., Hsinchu (TW)
Filed on Aug. 31, 2023, as Appl. No. 18/240,852.
Int. Cl. G11C 11/22 (2006.01); G11C 5/06 (2006.01); H10B 51/20 (2023.01); H10D 30/01 (2025.01); H10D 30/69 (2025.01)
CPC G11C 11/2275 (2013.01) [G11C 5/063 (2013.01); G11C 11/2273 (2013.01); H10B 51/20 (2023.02); H10D 30/0415 (2025.01); H10D 30/701 (2025.01)] 19 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) structure, comprising:
a substrate; and
a memory cell over the substrate, the memory cell comprising:
a channel layer;
a first doped region at a first side of the channel layer, the first doped region doped with a first dopant being of a first conductivity type;
a second doped region at a second side of the channel layer opposing the first side, the second doped region doped with a second dopant being of a second conductivity type different from the first conductivity type;
a first ferroelectric layer over the channel layer and between the first and second doped regions;
a second ferroelectric layer over the channel layer and spaced apart from the first ferroelectric layer by a non-zero distance;
a first gate layer over the first ferroelectric layer; and
a second gate layer over the second ferroelectric layer.