| CPC G09G 3/3275 (2013.01) [G09G 3/3266 (2013.01); G09G 2310/0297 (2013.01); G09G 2310/061 (2013.01); G09G 2310/08 (2013.01)] | 13 Claims |
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1. A display substrate comprising M rows and N columns of sub-pixels, N data signal lines and at least one data reset circuit, wherein at least one sub-pixel comprises a pixel circuit; an i-th data signal line is connected to an i-th column of pixel circuits, M≥1, N≥1 and 1≤i≤N; and
the data reset circuit, electrically connected to a data reset control terminal, a data initial signal terminal and the N data signal lines, is configured to provide a signal of the data initial signal terminal to the N data signal lines under control of the data reset control terminal,
wherein the at least one sub-pixel further comprises a light emitting element, and the pixel circuit is configured to drive the light emitting element to emit light;
the pixel circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and a capacitor;
a control electrode of the first transistor is connected to a reset signal terminal, a first electrode of the first transistor is connected to an initial signal terminal, and a second electrode of the first transistor is connected to a first node;
a control electrode of the second transistor is connected to a scan signal terminal, a first electrode of the second transistor is connected to the first node, and a second electrode of the second transistor is connected to a second node;
a control electrode of the third transistor is connected to the first node, a first electrode of the third transistor is connected to a third node, and a second electrode of the third transistor is connected to the second node;
a control electrode of the fourth transistor is connected to the scan signal terminal, a first electrode of the fourth transistor is connected to a data signal terminal, and a second electrode of the fourth transistor is connected to the third node;
a control electrode of the fifth transistor is connected to a light emitting signal terminal, a first electrode of the fifth transistor is connected to a first power supply terminal, and a second electrode of the fifth transistor is connected to the third node;
a control electrode of the sixth transistor is connected to the light emitting signal terminal, a first electrode of the sixth transistor is connected to the second node, and a second electrode of the sixth transistor is connected to a first electrode of the light emitting element;
a control electrode of the seventh transistor is connected to the reset signal terminal, a first electrode of the seventh transistor is connected to the initial signal terminal, and a second electrode of the seventh transistor is connected to the first electrode of the light emitting element; and
a first terminal of the capacitor is connected to the first power supply terminal, and a second terminal of the capacitor is connected to the first node;
the light emitting element is connected to the pixel circuit and a second power supply terminal respectively; and
the i-th data signal line is electrically connected to a data signal terminal of the i-th column of pixel circuits,
further comprising a multiplexer circuit, wherein
the multiplexer circuit, electrically connected to R multiplex control terminals, S data output terminals and the N data signal lines respectively, is configured to output signals of the S data output terminals to the N data signal lines in a way of time sharing under the control of the R multiplex control terminals, S=N/R and R is a positive integer greater than or equal to 2,
wherein for at least one pixel circuit, cut-off time before which the reset signal terminal receives active level signals is not later than start time at which the scan signal terminal receives the active level signals, and cut-off time before which the scan signal terminal receives the active level signals is not later than start time at which the light emitting signal terminal receives the active level signals;
time at which the R multiplex control terminals receive the active level signals is within time at which the scan signal terminal receives the active level signals, and there is no overlap among times at which different multiplex control terminals receive the active level signals; and
cut-off time before which an x-th multiplex control terminal receives the active level signals is not later than start time at which a (x+1)-th multiplex control terminal receives the active level signals, 1≤x≤R−1,
wherein time at which the data reset control terminal receives the active level signals does not overlap with the time at which the R multiplex control terminals receive the active level signals,
wherein the time at which the data reset control terminal receives the active level signals is within the time at which the scan signal terminal receives the active level signals.
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