US 12,254,838 B2
Shift register unit, gate driver circuit, and display device
Yonglin Guo, Beijing (CN); Zhiliang Jiang, Beijing (CN); Ming Hu, Beijing (CN); and Ziyang Yu, Beijing (CN)
Assigned to CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Sichuan (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Appl. No. 18/281,569
Filed by Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed Oct. 28, 2022, PCT No. PCT/CN2022/128105
§ 371(c)(1), (2) Date Sep. 12, 2023,
PCT Pub. No. WO2024/087130, PCT Pub. Date May 2, 2024.
Prior Publication US 2025/0029563 A1, Jan. 23, 2025
Int. Cl. G09G 3/32 (2016.01); G09G 3/3266 (2016.01); G11C 19/28 (2006.01)
CPC G09G 3/3266 (2013.01) [G11C 19/287 (2013.01); G09G 2310/0286 (2013.01); G09G 2320/02 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A shift register unit, comprising:
a first input circuit, coupled to a first clock terminal, an input terminal, a first node and a second node, and configured to control connection or disconnection between the input terminal and the first node in response to a first clock signal provided by the first clock terminal, and control connection or disconnection between the second node and the first node in response to a potential at the second node;
a second input circuit, coupled to the first node, the first clock terminal, a first power terminal and a third node, and configured to control connection or disconnection between the first clock terminal and the third node in response to a potential at the first node, and control connection or disconnection between the first power terminal and the third node in response to the first clock signal;
a first control circuit, coupled to the input terminal, the first clock terminal, the second node, a second power terminal, a second clock terminal and the third node, and configured to control connection or disconnection between the input terminal and the second node in response to the first clock signal, control connection or disconnection between the second power terminal and the second node in response to a potential at the third node, and control connection or disconnection between the second clock terminal and the second node in response to the potential at the second node;
a second control circuit, coupled to the third node, the second clock terminal, the first node, the first power terminal, the second power terminal, a fourth node and a fifth node, and configured to control connection or disconnection between the second clock terminal and the fourth node in response to the potential at the third node and a second clock signal provided by the second clock terminal, control connection or disconnection between the second power terminal and the fourth node in response to the potential at the first node, and control the first node to be connected to the fifth node in response to a first power signal provided by the first power terminal; and
an output circuit, coupled to the fourth node, the fifth node, the first power terminal, the second power terminal and an output terminal, and configured to control connection or disconnection between the second power terminal and the output terminal in response to a potential at the fourth node, and control connection or disconnection between the first power terminal and the output terminal in response to a potential at the fifth node.