| CPC G09G 3/3266 (2013.01) [G09G 3/3677 (2013.01); G09G 2300/0417 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/043 (2013.01); G09G 2310/0281 (2013.01); G09G 2320/0223 (2013.01); G09G 2320/0233 (2013.01)] | 17 Claims |
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1. A display panel, wherein the display panel comprises a pixel driving circuit and a gate driving circuit; the pixel driving circuit comprises a driving transistor; a gate of the driving transistor is connected to a gate line; the gate driving circuit is configured to provide a gate driving signal to the pixel driving circuit; and the display panel further comprises:
a substrate, wherein the substrate comprises a display region and a non-display region located on a side of the display region;
a second conductive layer, located on a side of the substrate, wherein the second conductive layer comprises:
more than one gate line, located in the display region, wherein an orthographic projection of the more than one gate line on the substrate extends along a row direction and is distributed at intervals in a column direction; and
more than one virtual gate line, located in the non-display region, wherein an orthographic projection of the more than one virtual gate line on the substrate extends along the row direction and is distributed at intervals in the column direction;
the display panel further comprises:
a virtual conductive part, located in the non-display region, wherein the virtual conductive part is located in a different conductive layer from the virtual gate line, an orthographic projection of the virtual conductive part on the substrate is located within an orthographic projection of the virtual gate line on the substrate, and the virtual conductive part is configured to form an equivalent capacitance with the virtual gate line;
wherein, a Resistor-Capacitor (RC) load of the virtual gate line matches with a RC load of the gate line;
the gate driving circuit comprises more than one first Gate driver On Array (GOA) unit and more than one second GOA unit, the first GOA unit is arranged corresponding to the gate line, and the first GOA unit is configured to provide a gate driving signal to the gate line of n-th row and a reset signal to the gate line of (n−i)-th row; and
the second GOA unit is arranged corresponding to the virtual gate line, one second GOA unit is connected to the virtual gate line of a row and provides a reset signal to the gate line of (N−i)-th row, n is a positive integer greater than or equal to 1 and less than or equal to N, i is a positive integer smaller than n, and N is a total number of rows of the gate line in the display region;
wherein the virtual gate line comprises a first side and a second side oppositely arranged in the column direction, and the virtual conductive part comprises a third side and a fourth side oppositely arranged in the column direction, a distance between an orthographic projection of the first side on the substrate and an orthographic projection of the second side on the substrate is L1, a distance between an orthographic projection of the third side on the substrate and an orthographic projection of the fourth side on the substrate is L2, and L1/L2 is greater than or equal to 1/10 and less than or equal to 1;
wherein the virtual gate line is provided with a first component part and a second component part, and a width of the first component part in the column direction is smaller than a width of the second component part in the column direction; and
the virtual conductive part comprises a first conductive sub-part and a second conductive sub-part, an orthographic projection of the first conductive sub-part on the substrate is located within an orthographic projection of the first component part on the substrate, an orthographic projection of the second conductive sub-part on the substrate is located within an orthographic projection of the second component part on the substrate.
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