| CPC G09G 3/3233 (2013.01) [G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2300/0861 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0247 (2013.01); G09G 2330/021 (2013.01); G09G 2340/0435 (2013.01)] | 20 Claims |
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1. A pixel circuit, comprising:
a first reset transistor, a compensation transistor, a drive transistor, a data writing transistor, a first light emitting control transistor, a second light emitting control transistor, a second reset transistor, a storage capacitor and a light emitting device; wherein:
the first reset transistor is coupled between a gate of the drive transistor and an initialization signal terminal, and a gate of the first reset transistor is coupled to a reset control terminal;
the compensation transistor is coupled between the gate and a first electrode of the drive transistor, and a gate of the compensation transistor is coupled to a first scan control terminal;
the data writing transistor is coupled between a second electrode of the drive transistor and a data signal terminal, and a gate of the data writing transistor is coupled to a second scan control terminal;
the first light emitting control transistor is coupled between the second electrode of the drive transistor and a first power supply terminal, and a gate of the first light emitting control transistor is coupled to a light emitting control terminal;
the second light emitting control transistor is coupled between the first electrode of the drive transistor and a first electrode of the light emitting device, and a gate of the second light emitting control transistor is coupled to the light emitting control terminal;
the second reset transistor is coupled between the first electrode of the light emitting device and the initialization signal terminal, and a gate of the second reset transistor is coupled to the second scan control terminal;
a second electrode of the light emitting device is coupled to a second power supply terminal;
the storage capacitor is coupled between the first power supply terminal and the gate of the drive transistor;
wherein the first scan control terminal is configured to receive a first scan control signal, the second scan control terminal is configured to receive a second scan control signal, an effective duration of the second scan control signal is greater than an effective duration of the first scan control signal, the effective duration of the first scan control signal is covered by the effective duration of the second scan control signal, the data signal terminal is configured to receive a constant reset signal within other effective duration of the second scan control signal except a covered part, and the data signal terminal is configured to receive a data signal within a duration of the covered part.
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