| CPC G09G 3/32 (2013.01) [G09G 3/30 (2013.01); G09G 3/3208 (2013.01); H05B 45/345 (2020.01); G09G 2310/0202 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/0294 (2013.01); G09G 2320/0693 (2013.01); G09G 2330/08 (2013.01); H05B 45/20 (2020.01)] | 4 Claims |

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1. A dual-line cascade application system for simultaneously supplying electrical power and transmitting data comprising a controller, cascade chips and LED lights; the controller is connected to the cascade chips; the cascade chips are connected to the LED lights; each of the cascade chips is provided with a voltage clamp module, an electrical power supply module, a data storage module, a PWM constant current output driving circuit, an R end, a G end, a B end, a W end, a VCC/DATA end and a GND/DATA end, as well as a data sampling and calibration module, a power line data sampling and transmission module, a chip initial address setting by command module, a module which determines if E-fuse address of the corresponding cascade chip is identical to an address of received data, and an E-fuse module; the VCC/DATA end is connected to the voltage clamp module, the data sampling and calibration module and the power line data sampling and transmission module respectively; the voltage clamp module has output ends which are connected to the GND/DATA end and the electrical power supply module respectively; the electrical power supply module has an output end which is connected to the data sampling and calibration module, the power line data sampling and transmission module, the chip initial address setting by command module, the E-fuse module, the data storage module and the PWM constant current output driving circuit respectively to supply power; the power line data sampling and transmission module has an output end which is connected to the chip initial address setting by command module, the E-fuse module, and the data storage module respectively; an output end of the module which determines if E-fuse address of the corresponding cascade chip is identical to the address of received data is connected to the data storage module; input ends of the module which determines if E-fuse address of the chip is identical to an address of received data are connected to the chip initial address setting by command module and the E-fuse module respectively; the PWM constant current output driving circuit is connected to the R end, the G end, the B end and the W end;
each of the cascade chips is further provided with an oscillation circuit and a reset circuit; the oscillation circuit and the reset circuit are connected between the electrical power supply module and the power line data sampling and transmission module.
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