| CPC G09G 3/32 (2013.01) [G09G 2300/0452 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2310/0202 (2013.01); G09G 2310/0297 (2013.01); G09G 2310/08 (2013.01); G09G 2330/021 (2013.01)] | 17 Claims |

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1. A display panel, comprising:
a plurality of light-emitting pixels arranged in an array;
at least one demultiplexing circuit, for each of the at least one demultiplexing circuit, an input end being connected to a data signal fan-out line, and two output ends being respectively connected to two data signal lines;
a first strobe signal line for providing a first strobe signal and a second strobe signal line for providing a second strobe signal; and
at least one data signal fan-out line, each of the at least one data signal fan-out line electrically connected to an input end of a corresponding one of the at least one demultiplexing circuit;
wherein
in an nth line scanning stage, the first strobe signal is switched from a disable signal to an enable signal at a first time node, and the second strobe signal is switched from the enable signal to the disable signal at a second time node;
in the nth line scanning stage, each of the at least one data signal fan-out line outputs a first data voltage in a first data signal stage, and outputs a second data voltage in a second data signal stage; and the first data signal stage overlaps partially an enable signal period of the first strobe signal, and the second data signal stage overlaps partially an enable signal period of the second strobe signal;
at the end of the nth line scanning stage, the first strobe signal and the second strobe signal remain unchanged;
in an (n+1)th line scanning stage, the first strobe signal is switched from the enable signal to the disable signal at a third time node, and the second strobe signal is switched from the disable signal to the enable signal at a fourth time node;
in the (n+1)th line scanning stage, each of the at least one data signal fan-out line outputs a third data voltage in a third data signal stage, and outputs a fourth data voltage in a fourth data signal stage; and the third data signal stage overlaps partially the enable signal period of the first strobe signal, and the fourth data signal stage overlaps partially the enable signal period of the second strobe signal;
an overlapping time period between the first data signal stage and the enable signal period of the first strobe signal is greater than that between the third data signal stage and the enable signal period of the first strobe signal; and
a first control end and a second control end of each of the least one demultiplexing circuit are connected to the first strobe signal line and the second strobe signal line respectively.
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