| CPC G09G 3/32 (2013.01) [G09G 3/3258 (2013.01); G09G 2300/0828 (2013.01); G09G 2300/0852 (2013.01); G09G 2300/0861 (2013.01); G09G 2310/0259 (2013.01); G09G 2310/066 (2013.01); G09G 2320/0626 (2013.01); G09G 2320/0693 (2013.01); G09G 2360/10 (2013.01)] | 17 Claims |

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1. A picture element for a display device, comprising
a first and a second supply terminal,
a light-emitting semiconductor device arranged between the first and the second supply terminal,
a comparison unit having a first and a second input and an output, the comparison unit being configured to adjust a voltage at the output in dependence on a comparison of a voltage applied to the first input and a voltage applied to the second input,
a supply switch configured to control a current flow between the first and the second supply terminal via the light-emitting semiconductor device depending on the voltage applied at the output of the comparison unit,
a selection input and a data input,
a memory element and a control switch which is configured to supply a data signal provided via the data input to the first input of the comparison unit as a function of a selection signal applied to the selection input and to hold the data signal in the memory element, the second input of the comparison unit being configured to receive a ramp signal so that a current flow through the light-emitting semiconductor device can be set as a function of the data signal,
wherein the data signal comprises a predetermined number N of digital data bits, the memory element has a plurality of N data capacitors corresponding to the predetermined number N of digital data bits, and the control switch has a plurality of N control units corresponding to the predetermined number N of digital data bits,
inputs of the plurality of N control units are coupled to the data input,
the plurality of N control units and the plurality of N data capacitors form a plurality of N sample-and-hold units,
outputs of the plurality of N sample-and-hold units are coupled to N terminals of the first input of the comparison unit, and
depending on the significance of the individual data bits, a correspondingly staggered multiplier is connected downstream of the N terminals of the first input within the comparison unit before multiplied voltages are fed to an adder within the comparison unit and the result is compared with the ramp signal applied to the second input of the comparison unit.
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