| CPC G09G 3/2092 (2013.01) [H03K 19/00361 (2013.01); G09G 2300/0426 (2013.01); G09G 2310/0291 (2013.01); G09G 2310/08 (2013.01); G09G 2330/021 (2013.01); G09G 2330/06 (2013.01)] | 13 Claims |
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1. An output buffer circuit for outputting an output signal in which a binary input signal is amplified from an output terminal, the output buffer circuit comprising:
a bias part, generating a bias current; and
a buffer part, generating a mirror current of the bias current, receiving the input terminal, and generating the output signal,
wherein the buffer part has:
a first transistor of a first conductivity type, supplying a first power voltage to the output terminal in a case of becoming an ON state in accordance with a voltage of the input signal received by a gate of the first transistor;
a second transistor of a second conductivity type, supplying a second power voltage to the output terminal in a case of becoming the ON state in accordance with the voltage of the input signal received by a gate of the second transistor, the second power voltage being lower than the first power voltage; and
an output control part, transitioning a transistor in an OFF state between the first transistor and the second transistor to the ON state by changing a voltage of the gate of the transistor in the OFF state at a change speed based on a current value of the mirror current when the voltage of the input signal changes,
wherein, in accordance with a voltage change of the input signal, the bias part sets a current value of the bias current to a first current value throughout a predetermined period, and switches the current value of the bias current to a second current value smaller than the first current value in periods other than the predetermined period.
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