US 12,254,808 B2
Gate drive circuits and display panels
Bin Yuan, Hubei (CN); Fang Qin, Hubei (CN); and Cheng Chen, Hubei (CN)
Assigned to WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD., Wuhan (CN)
Filed by WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD., Hubei (CN)
Filed on Apr. 6, 2024, as Appl. No. 18/628,691.
Application 18/628,691 is a continuation of application No. 18/357,252, filed on Jul. 24, 2023, granted, now 12,008,940.
Application 18/357,252 is a continuation of application No. PCT/CN2023/089515, filed on Apr. 20, 2023.
Claims priority of application No. 202310206893.4 (CN), filed on Mar. 1, 2023.
Prior Publication US 2024/0296770 A1, Sep. 5, 2024
Int. Cl. G09G 3/20 (2006.01); H03K 17/687 (2006.01)
CPC G09G 3/20 (2013.01) [H03K 17/6872 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0852 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01); G09G 2330/021 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A display panel, comprising:
a gate drive circuit, comprising M cascaded gate drive units, wherein at least one of the gate drive units comprises a first output stage configured to output a first gate control signal and a second output stage configured to output a second gate control signal, and wherein M is an integer greater than 1 and N is an integer greater than 0 and less than M; and
a pixel circuit connected to an N-th stage gate drive unit of the at least one of the gate drive units and comprising at least a first thin film transistor and a second thin film transistor, wherein the first thin film transistor has a channel type different from that of the second thin film transistor, and wherein a gate of the first thin film transistor and a gate of the second thin film transistor are connected to the first output stage and the second output stage of N-th stage gate drive unit to receive the first gate control signal and the second gate control signal, respectively,
wherein a number of pulses and a pulse width of the second gate control signal in one frame both are different from a number of pulses and a pulse width of the first gate control signal in the one frame.