US 12,254,806 B2
Display panel, driving method thereof, and display device
Jujian Fu, Wuhan (CN)
Assigned to Hubei Yangtze Industrial Innovation Center Of Advanced Display Co., Ltd., Wuhan (CN)
Filed by Hubei Yangtze Industrial Innovation Center Of Advanced Display Co., Ltd., Wuhan (CN)
Filed on Dec. 1, 2023, as Appl. No. 18/526,403.
Application 18/526,403 is a continuation of application No. 18/089,692, filed on Dec. 28, 2022, granted, now 11,869,404.
Claims priority of application No. 202210760958.5 (CN), filed on Jun. 29, 2022.
Prior Publication US 2024/0112610 A1, Apr. 4, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G09G 3/20 (2006.01); G09G 3/32 (2016.01); G09G 3/3233 (2016.01)
CPC G09G 3/20 (2013.01) [G09G 3/32 (2013.01); G09G 3/3233 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2300/0861 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0233 (2013.01); G09G 2340/0435 (2013.01); G09G 2360/16 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A display panel, comprising: a light-emitting element and a pixel circuit electrically connected to the light-emitting element, wherein
the pixel circuit comprises a drive transistor and a first transistor, a first terminal of the drive transistor is electrically connected to a power signal line, a first terminal of the first transistor is electrically connected to an initialization signal line; wherein a second terminal of the first transistor is electrically connected to the drive transistor, or the second terminal of the first transistor is electrically connected to the light-emitting element;
drive modes of the display panel comprise an i-th drive mode and a j-th drive mode, and the j-th drive mode comprises a signal writing stage and a light emission holding stage, wherein i and j are both integers, and i≠j; and
the i-th drive mode corresponds to an i-th drive frequency Fi and an i-th initialization signal Vrefi, the j-th drive mode corresponds to a j-th drive frequency Fj, the signal writing stage in the j-th drive mode corresponds to a j1-th initialization signal Vrefj1, and the light emission holding stage in the j-th drive mode corresponds to a j2-th initialization signal Vrefj2;
wherein Fj<Fi, and |Vrefj2|>|Vrefj1|>|Vrefi|.