US 12,254,805 B1
Pixel driving circuit and display panel
Maoxia Zhu, Guangdong (CN)
Assigned to GUANGZHOU CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD., Guangdong (CN)
Filed by GUANGZHOU CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD., Guangdong (CN)
Filed on Nov. 29, 2023, as Appl. No. 18/523,423.
Claims priority of application No. 202311344424.5 (CN), filed on Oct. 17, 2023.
Int. Cl. G09G 3/3225 (2016.01); G09G 3/20 (2006.01)
CPC G09G 3/20 (2013.01) [G09G 2300/0819 (2013.01); G09G 2300/0852 (2013.01); G09G 2310/08 (2013.01); G09G 2320/045 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A pixel driving circuit, comprising: a light-emitting module, an external detection module, and an internal compensation module, wherein the light-emitting module is electrically connected to the external detection module and the internal compensation module;
wherein the light-emitting module comprises a second transistor and a light-emitting unit, a first electrode of the second transistor is electrically connected to a high-electric potential power supply signal, and a second electrode of the second transistor is electrically connected to the light-emitting unit;
the external detection module is configured to acquire a threshold voltage of the second transistor when a display panel is turned on, and determine a shift direction of the threshold voltage; and
the internal compensation module is configured to use a first timing sequence to compensate the threshold voltage when the shift direction of the threshold voltage is a positive shift; the internal compensation module is configured to use a second timing sequence to compensate the threshold voltage when the shift direction of the threshold voltage is a negative shift; and the first timing sequence is different from the second timing sequence;
wherein the pixel driving circuit is a 9T3C circuit, the light-emitting module further comprises a first transistor, a third transistor, and a first capacitor, a gate of the first transistor is input with a first light-emitting signal, a first electrode of the first transistor is input with a high-electric potential power supply signal, a second electrode of the first transistor is connected to the first electrode of the second transistor, the second electrode of the second transistor is connected to a second electrode of the third transistor, a first electrode of the third transistor is connected to an anode of the light-emitting unit, a gate of the third transistor is input with a second light-emitting signal, a cathode of the light-emitting unit is input with a low-electric potential power supply signal, one terminal of the first capacitor is connected to the first electrode of the first transistor, and another terminal of the first capacitor is connected to the second electrode of the second transistor;
the external detection module comprises a first switch, a second switch, a chip, and a fourth transistor, a gate of the fourth transistor is input with a first scan signal, and a second electrode of the fourth transistor is electrically connected to the second electrode of the second transistor, a first electrode of the fourth transistor is connected to the chip through a first branch and a second branch arranged in parallel, the first branch comprises the first switch, and the second branch comprises the second switch;
the internal compensation module comprises a third capacitor, a fifth transistor, a seventh transistor, an eighth transistor, and a ninth transistor, one terminal of the third capacitor is connected to a gate of the second transistor, and another terminal of the third capacitor is connected to the second electrode of the second transistor, a gate of the fifth transistor is input with the first scan signal, a second electrode of the fifth transistor is electrically connected to a second electrode of the ninth transistor, a first electrode of the fifth transistor is connected to the second electrode of the first transistor, a first electrode of the ninth transistor is connected to the first electrode of the first transistor, and a gate of the ninth transistor is input with a third scan signal, a second electrode of the seventh transistor is connected to the second electrode of the ninth transistor, a first electrode of the seventh transistor is electrically connected to the gate of the second transistor, a gate of the seventh transistor is input with a fourth scan signal, a gate of the eighth transistor is input with a fifth scan signal, a first electrode of the eighth transistor is input with a second data signal, and a second electrode of the eighth transistor is connected to the gate of the second transistor.