US 12,254,613 B2
Systems and methods for inspection of IC devices
Nicholas Darby, Columbus, OH (US); Jeremiah Schley, Dublin, OH (US); and Jeremy Bellay, Columbus, OH (US)
Assigned to Battelle Memorial Institute, Columbus, OH (US)
Filed by Battelle Memorial Institute, Columbus, OH (US)
Filed on Feb. 14, 2024, as Appl. No. 18/441,669.
Application 18/441,669 is a continuation of application No. 17/685,837, filed on Mar. 3, 2022, granted, now 11,941,797.
Claims priority of provisional application 63/156,218, filed on Mar. 3, 2021.
Prior Publication US 2024/0185408 A1, Jun. 6, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06K 9/00 (2022.01); G06T 1/00 (2006.01); G06T 7/00 (2017.01)
CPC G06T 7/0006 (2013.01) [G06T 1/0007 (2013.01); G06T 2207/20081 (2013.01); G06T 2207/20084 (2013.01); G06T 2207/30148 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A computer-implemented method for inspecting ICs, the computer-implemented method comprising:
receiving, by a controller, one or more images of a Device Under Test (DUT) from one or more imaging devices;
detecting, by the controller, observed features in the one or more images and producing a first synthetic representation of a part design of the DUT that includes the observed features;
inferring, by the controller, a presence of one or more first unobserved features; and
adding, by the controller, the one or more first unobserved features to the first synthetic representation of the part design of the DUT.