US 12,254,527 B2
Reconfigurable virtual graphics and compute processor pipeline
Timour T. Paltashev, Santa Clara, CA (US); Michael Mantor, Orlando, FL (US); and Rex Eldon McCrary, Orlando, FL (US)
Assigned to Advanced Micro Devices, Inc., Sunnyvale, CA (US)
Filed by ADVANCED MICRO DEVICES, INC., Santa Clara, CA (US)
Filed on May 21, 2020, as Appl. No. 16/879,991.
Application 16/879,991 is a continuation of application No. 15/331,278, filed on Oct. 21, 2016, granted, now 10,664,942.
Prior Publication US 2021/0049729 A1, Feb. 18, 2021
Int. Cl. G06T 1/20 (2006.01); G06T 1/60 (2006.01); G06T 15/00 (2011.01); G06T 15/80 (2011.01); G06T 17/10 (2006.01)
CPC G06T 1/20 (2013.01) [G06T 15/005 (2013.01); G06T 1/60 (2013.01); G06T 15/80 (2013.01); G06T 17/10 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a plurality of shared resources comprising:
a plurality of programmable processing cores configured to process graphics primitives and corresponding data; and
a plurality of fixed-function hardware units, wherein the shared resources are allocated to implement a configurable number of virtual graphics pipelines, wherein
the virtual graphics pipelines are to concurrently execute commands that are fed to each virtual graphics pipeline using at least one buffer;
each virtual graphics pipeline includes a number of shared resources dynamically configurable in response to at least one of a system event or user input;
each virtual graphics pipeline is mapped to memory hierarchy resources of the apparatus based on a mapping that is dynamically adjustable in response to one or more of at least one of system event or at least one user input; and
the virtual graphics pipelines are reconfigured in response to one or more at least one system event or at least one user input.