US 12,254,397 B2
Apparatus of implementing activation logic for neural network and method thereof
Woon-Sik Suh, New Taipei (CN)
Appl. No. 17/291,315
Filed by GENESYS LOGIC, INC., New Taipei (CN)
PCT Filed May 16, 2019, PCT No. PCT/CN2019/087299
§ 371(c)(1), (2) Date May 5, 2021,
PCT Pub. No. WO2020/093676, PCT Pub. Date May 14, 2020.
Claims priority of provisional application 62/756,095, filed on Nov. 6, 2018.
Prior Publication US 2022/0004850 A1, Jan. 6, 2022
Int. Cl. G06N 3/063 (2023.01); G06F 1/03 (2006.01); G06F 7/50 (2006.01); G06F 7/523 (2006.01); G06F 7/53 (2006.01); G06F 7/544 (2006.01); G06F 9/54 (2006.01); G06N 3/048 (2023.01); G06N 3/08 (2023.01)
CPC G06N 3/063 (2013.01) [G06F 1/03 (2013.01); G06F 7/50 (2013.01); G06F 7/523 (2013.01); G06F 7/53 (2013.01); G06F 7/5443 (2013.01); G06F 9/54 (2013.01); G06N 3/048 (2023.01); G06N 3/08 (2013.01)] 33 Claims
OG exemplary drawing
 
1. An apparatus of implementing activation logic for a neural network comprises a processor and a memory, wherein the memory is configured to store executable program instructions, and the processor is configured to execute the executable program instructions, the apparatus comprising:
an input circuit comprising n bits and n input data values that are stored in the n bits correspondingly, wherein n is defined as a sum of n1 and n2, and n, n1, and n2 are positive integers;
a first address translated look-up table circuit comprising (2 n1) first entries that map to (2 n1) bit addresses based on the n bits of the input circuit, wherein each of the (2 n1) first entries comprises (n1−1) bits and (n1−1) first preset values stored in the (n1−1) bits correspondingly, and n1 input data values of the n bits of the input circuit are mapped to the (n1−1) first preset values that stored in one of the (2 n1) first entries of the first address translated look-up table circuit;
an intermediate storage circuit coupled to the input circuit and the first address translated look-up table circuit, wherein the intermediate storage circuit comprises (n−1) bits by combining the (n1−1) bits of the first address translated look-up table circuit with n2 bits of the input circuit, and comprises (n−1) intermediate data values by combining the (n1−1) first preset values of the first address translated look-up table circuit with n2 input data values of the n bits of the input circuit;
a second address translated look-up table circuit comprising (2 (n−1)) second entries that map to (2 (n−1)) bit addresses based on of the (n−1) bits of the intermediate storage circuit, wherein each of the (2 (n−1)) second entries comprises (n2+1) bits and (n2+1) second preset values stored in the (n2+1) bits correspondingly, and the (n−1) intermediate data values of the (n−1) bits of the intermediate storage circuit are mapped to the (n2+1) second preset values stored in one of the (2 (n−1)) second entries of the second address translated look-up table circuit; and
an output circuit coupled to the first address translated look-up table circuit and the second address translated look-up table circuit, combining the (n1−1) bits of the first address translated look-up table circuit with the (n2+1) bits of the second address translated look-up table circuit for outputting n output data values by combining the (n1−1) first preset values and the (n2+1) second preset values.