US 12,254,321 B2
Method of resetting integrated circuit with synchronous reset signal, and integrated circuit
Chongyang Wang, Shenzhen (CN); Chen Lin, Shenzhen (CN); Huafeng Xu, Shenzhen (CN); and Bin Guo, Shenzhen (CN)
Assigned to SANECHIPS TECHNOLOGY CO., LTD., Shenzhen (CN)
Appl. No. 18/022,303
Filed by SANECHIPS TECHNOLOGY CO., LTD, Shenzhen (CN)
PCT Filed Aug. 19, 2021, PCT No. PCT/CN2021/113490
§ 371(c)(1), (2) Date Feb. 21, 2023,
PCT Pub. No. WO2022/037638, PCT Pub. Date Feb. 24, 2022.
Claims priority of application No. 202010848569.9 (CN), filed on Aug. 21, 2020.
Prior Publication US 2023/0325199 A1, Oct. 12, 2023
Int. Cl. G06F 9/4401 (2018.01)
CPC G06F 9/4403 (2013.01) 20 Claims
OG exemplary drawing
 
1. A method of resetting an integrated circuit, comprising:
generating, in response to a reset signal intended for a first data unit comprised in the integrated circuit, a synchronous reset signal based on the reset signal, and outputting the synchronous reset signal to the first data unit after at least one preset period, wherein the synchronous reset signal is used for resetting the first data unit, and the synchronous reset signal is delayed by N preset periods relative to the reset signal, N being greater than or equal to 2; and
generating, in response to a first data signal output by the first data unit and intended for a second data unit comprised in the integrated circuit, a second data signal based on the synchronous reset signal and the first data signal, and outputting the second data signal to the second data unit, wherein the first data unit and the second data unit belong to different reset domains.