US 12,254,319 B2
Scalable toggle point control circuitry for a clustered decode pipeline
Sundararajan Ramakrishnan, Cedar Park, TX (US); Jonathan Combs, Austin, TX (US); Martin J. Licht, Round Rock, TX (US); and Santhosh Srinath, Menlo Park, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 24, 2021, as Appl. No. 17/484,969.
Prior Publication US 2023/0099989 A1, Mar. 30, 2023
Int. Cl. G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 11/07 (2006.01)
CPC G06F 9/30145 (2013.01) [G06F 9/3812 (2013.01); G06F 9/3814 (2013.01); G06F 9/3822 (2013.01); G06F 11/0757 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A hardware processor core comprising:
a first decode cluster comprising a plurality of decoder circuits;
a second decode cluster comprising a plurality of decoder circuits; and
a toggle point control circuit to toggle between sending instructions requested for decoding between the first decode cluster and the second decode cluster, wherein the toggle point control circuit is to:
determine a location in an instruction stream as a candidate toggle point to switch the sending of the instructions requested for decoding between the first decode cluster and the second decode cluster,
track a number of times a characteristic of multiple previous decodes of the instruction stream is present for the location, and
cause insertion of a toggle point at the location, based on the number of times, to switch the sending of the instructions requested for decoding between the first decode cluster and the second decode cluster.