| CPC G06F 9/3013 (2013.01) [G06F 9/30058 (2013.01); G06F 9/3861 (2013.01)] | 20 Claims |
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1. A method comprising:
determining an original instruction associated with a first logical register which is mapped to a first physical register, wherein the first physical register is initially marked as eligible for early release;
determining a current instruction associated with a current logical register and one or more operands with corresponding values produced by one or more prior instructions, wherein a prior instruction is associated with a second logical register which is mapped to a second physical register;
allocating the current logical register to a third physical register;
responsive to determining that the current instruction and the prior instruction are executed in different iterations, marking the second physical register as not eligible for early release;
responsive to determining that the current logical register is previously mapped to the first physical register, determining that the allocation comprises a redefinition of the first logical register;
responsive to determining that the first physical register is eligible for early release and that the current instruction and the original instruction are executed in the same iteration or consecutive iterations, releasing the first physical register based upon the redefinition of the first logical register, irrespective of whether the prior instruction has completed execution or the current instruction has been committed; and
indicating that the first physical register is early released, thereby facilitating speculative reclamation of physical registers and reducing a size of a corresponding physical register file.
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