US 12,254,316 B2
Vector processor architectures
Martin Langhammer, Alderbury (GB); Eriko Nurvitadhi, Hillsboro, OR (US); and Gregg William Baeckler, San Jose, CA (US)
Assigned to Altera Corporation, San Jose, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 26, 2021, as Appl. No. 17/214,646.
Claims priority of provisional application 63/072,095, filed on Aug. 28, 2020.
Prior Publication US 2021/0216318 A1, Jul. 15, 2021
Int. Cl. G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 9/445 (2018.01); G06F 30/347 (2020.01)
CPC G06F 9/30036 (2013.01) [G06F 9/30038 (2023.08); G06F 9/30098 (2013.01); G06F 9/3887 (2013.01); G06F 9/38873 (2023.08); G06F 9/3888 (2023.08); G06F 9/44505 (2013.01); G06F 30/347 (2020.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit device comprising:
a plurality of vector registers configurable to store a plurality of vectors;
first switch circuitry communicatively coupled to the plurality of vector registers, wherein the first switch circuitry is configurable to receive the plurality of vectors directly from the plurality of vector registers and route a portion of the plurality of vectors to a plurality of vector processing units, wherein the plurality of vector processing units respectively comprise second switch circuitry configurable to route data within the plurality of vector processing units and are communicatively coupled to the first switch circuitry and configurable to:
receive the portion of the plurality of vectors directly from the first switch circuitry;
perform one or more operations involving the portion of the plurality of vectors; and
output a second plurality of vectors generated by performing the one or more operations; and
third switch circuitry communicatively coupled to the plurality of vector processing units and the plurality of vector registers, wherein the third switch circuitry is configurable to:
receive the second plurality of vectors directly from the plurality of vector processing units; and
route the second plurality of vectors to the plurality of vector registers.