US 12,254,284 B2
Multiplication-and-accumulation circuits and processing-in-memory devices having the same
Choung Ki Song, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on May 13, 2021, as Appl. No. 17/319,717.
Claims priority of application No. 10-2021-0003632 (KR), filed on Jan. 11, 2021.
Prior Publication US 2022/0222044 A1, Jul. 14, 2022
Int. Cl. G06F 7/544 (2006.01); G06F 7/487 (2006.01); G06F 7/501 (2006.01); G11C 7/10 (2006.01)
CPC G06F 7/5443 (2013.01) [G06F 7/4876 (2013.01); G06F 7/501 (2013.01); G11C 7/1012 (2013.01); G11C 7/106 (2013.01); G11C 7/1087 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A multiplication-and-accumulation MAC circuit comprising:
a MAC operator circuit comprising:
a multiplier circuit including a plurality of multipliers, a data output selection circuit including a plurality of demultiplexers, and an adder circuit including an adder tree, first and second inputs of the multiplier circuit being configured to receive weight data and vector data from memory, the MAC operator circuit being additionally configured to selectively perform at least one of:
a MAC arithmetic operation when the MAC operator circuit receives the weight data and the vector data, and
an element-wise multiplication EWM arithmetic operation when the MAC operator circuit receives the weight data and constant data; and
a data input circuit
configured to provide the MAC operator circuit with the weight data when the MAC operator circuit performs at least one of the MAC arithmetic operation and the element-wise multiplication (EWM) arithmetic operation, and
configured to selectively provide the MAC operator circuit one of the vector data or constant data when the MAC operator performs the EWM arithmetic operation;
wherein the MAC operator circuit selectively performs the MAC arithmetic operation and the element-wise multiplication EWM responsive to a control signal provided to the MAC circuit, and
wherein the control signal is input to the MAC operator circuit and the data input circuit in common.