| CPC G06F 7/5443 (2013.01) [G06N 3/063 (2013.01); G11C 8/10 (2013.01)] | 29 Claims |

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1. An arithmetic device comprising:
an activation function (AF) control circuit configured to generate a column address, a data selection signal, and an internal control signal based on an arithmetic result signal and an activation control signal during an activation operation;
a data storage circuit configured to output activation data from a memory cell array that is selected by the column address and a row address;
an output distribution signal generation circuit configured to generate an output distribution signal from the activation data based on the data selection signal and the internal control signal, and
an interpolation circuit configured to perform an interpolation operation based on the arithmetic result signal and the activation data when an activation function is applied to a multiplying-and-accumulating (MAC) arithmetic operation.
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