| CPC G06F 30/398 (2020.01) [H01L 29/66462 (2013.01); G06F 2119/02 (2020.01); G06F 2119/18 (2020.01)] | 20 Claims | 

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               1. A calibration method for emulating a Group III-V semiconductor device comprising: 
            establishing a process emulation program according to an actual process flow of the Group III-V semiconductor device and running the process emulation program to obtain an emulated Group III-V semiconductor device with emulated electrical performances; 
                performing actual tape-out according to the actual process flow of the Group III-V semiconductor device to form actual Group III-V semiconductor devices; 
                obtaining actual electrical performances of the actual Group III-V semiconductor devices and comparing the actual electrical performances with the emulated electrical performances to find discrepancies between the actual electrical performances and the emulated electrical performances; 
                performing a failure analysis to the actual Group III-V semiconductor devices to identify one or more locations where failure is found; and 
                calibrating the process emulation program by inserting one or more traps at the locations in the emulated Group III-V semiconductor device to obtain calibrated emulated electrical performances of the emulated Group III-V semiconductor device until the calibrated emulated electrical performances are consistent with the actual electrical performances. 
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