| CPC G06F 30/394 (2020.01) [G06F 30/392 (2020.01)] | 20 Claims |

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1. A method comprising:
designing a plurality of cells for a semiconductor device, wherein designing the plurality of cells comprises reserving a routing track within each of the plurality of cells, wherein each of the plurality of cells comprises signal lines for connection to elements within the cell, each of the plurality of cells further comprises a plurality of routing tracks, the reserved routing track is one of the plurality of routing tracks, and the reserved routing track is free of the signal lines;
placing a first cell of the plurality of cells in a layout of the semiconductor device;
placing a second cell of the plurality of cells in the layout;
determining whether any power rails overlap with any of the plurality of routing tracks other than the reserved routing track in the second cell; and
adjusting a distance between the first cell and the second cell in response to a determination that at least one power rail overlaps with at least one routing track of the plurality of routing tracks other than the reserved routing track for the second cell.
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