US 12,254,260 B2
Systems and methods for integrated circuit layout
Sheng-Hsiung Chen, Zhubei (TW); Chun-Chen Chen, Hsinchu (TW); Shao-huan Wang, Hsinchu (TW); Kuo-Nan Yang, Hsinchu (TW); Chung-Hsing Wang, Hsinchu (TW); Ren-Zheng Liao, Hsinchu (TW); and Meng-Xiang Lee, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed on Jul. 28, 2023, as Appl. No. 18/361,467.
Application 18/361,467 is a continuation of application No. 16/746,029, filed on Jan. 17, 2020, granted, now 11,748,542.
Prior Publication US 2024/0020451 A1, Jan. 18, 2024
Int. Cl. G06F 30/392 (2020.01); G06F 30/327 (2020.01); G06F 30/3312 (2020.01); G06F 30/367 (2020.01); G06F 30/398 (2020.01); G06F 111/04 (2020.01); G06F 117/12 (2020.01); G06F 119/06 (2020.01); G06F 119/12 (2020.01)
CPC G06F 30/392 (2020.01) [G06F 30/327 (2020.01); G06F 30/3312 (2020.01); G06F 30/367 (2020.01); G06F 30/398 (2020.01); G06F 2111/04 (2020.01); G06F 2117/12 (2020.01); G06F 2119/06 (2020.01); G06F 2119/12 (2020.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit layout, comprising:
a space arranged for an integrated circuit layout; and
wherein the space comprises:
a first area consisting of a plurality of first cell rows partially extending across the space along a first direction, each of the first cell rows having a first height along a second direction perpendicular to the first direction; and
a second area consisting of a plurality of second cell rows partially extending across the space along the first direction, each of the one or more second cell rows having a second height along the second direction, the second height different from the first height,
wherein each of the first cell rows has a pair of first power rails extending along its edges, respectively, and each of the second cell rows has a pair of second power rails extending along its edges, respectively.