US 12,254,259 B2
Multi-row standard cell design method in hybrid row height system
Hung-Chih Ou, Kaohsiung (TW); Wen-Hao Chen, Hsinchu (TW); and Chun-Yao Ku, Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed on Jan. 21, 2022, as Appl. No. 17/580,706.
Application 17/580,706 is a continuation of application No. 16/744,311, filed on Jan. 16, 2020.
Prior Publication US 2022/0147687 A1, May 12, 2022
Int. Cl. G06F 30/392 (2020.01)
CPC G06F 30/392 (2020.01) 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) layout, the IC layout comprising:
a plurality of rows of at least two different row-heights;
a discrete multi-row cell deployed over the plurality of rows, the multi-row cell comprising:
a first sub-cell deployed on at least a first row of cells with a first row-height;
a second sub-cell deployed on at least a second row of cells with a second row-height, and
empty spaces surrounding the first and second sub-cells,
wherein the first row and the second row have different number of fins corresponding to at least two different row-heights,
wherein the empty spaces are used for filling in other cells of matching geometry,
wherein the multi-row cell comprises a sub-cell covering more than one row, and
wherein the first sub-cell and the second sub-cell are electrically connected by at least a wire in the empty spaces.