US 12,254,256 B2
Diagnosis of inconsistent constraints in a power intent for an integrated circuit design
Maheshwar Chandrasekar, Santa Clara, CA (US); Brian T. Selden, Hilo, HI (US); and Makarand V. Patil, Portland, OR (US)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Mountain View, CA (US)
Filed on Jul. 13, 2022, as Appl. No. 17/864,232.
Claims priority of provisional application 63/222,326, filed on Jul. 15, 2021.
Prior Publication US 2023/0016865 A1, Jan. 19, 2023
Int. Cl. G06F 30/3323 (2020.01); G06F 30/31 (2020.01); G06F 30/398 (2020.01); G06F 111/04 (2020.01); G06F 119/06 (2020.01)
CPC G06F 30/3323 (2020.01) [G06F 30/31 (2020.01); G06F 30/398 (2020.01); G06F 2111/04 (2020.01); G06F 2119/06 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
loading a power intent on an integrated circuit (IC) design, wherein the power intent is represented by a set of constraints;
constructing a logic network based on the set of constraints and a rule check which is desired to be performed on the power intent;
performing the rule check on the power intent using the logic network;
in response to a failure of the rule check, creating one or more refutation proofs based on the logic network; and
identifying, by a processor, a subset of the set of constraints based on the one or more refutation proofs, wherein the subset of the set of constraints includes an inconsistency which caused the rule check to fail.