US 12,254,255 B1
Glitch identification and power analysis using simulation vectors
Joydeep Banerjee, Karnataka (IN); Mayur Bubna, Karnataka (IN); Debabrata Das Roy, Karnataka (IN); and Solaiman Rahim, San Francisco, CA (US)
Assigned to SYNOPSYS, INC., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Sunnyvale, CA (US)
Filed on Jun. 10, 2022, as Appl. No. 17/837,954.
Int. Cl. G06F 30/3315 (2020.01); G06F 30/3312 (2020.01); G06F 119/06 (2020.01); G06F 119/12 (2020.01)
CPC G06F 30/3315 (2020.01) [G06F 30/3312 (2020.01); G06F 2119/06 (2020.01); G06F 2119/12 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
receiving a simulation vector associated with a circuit design, wherein the simulation vector is associated with a simulation vector type;
identifying, by a processor, a plurality of glitch transitions from among one or more transitions associated with a pin of a cell of the circuit design during a clock period of the simulation vector; and
determining a glitch power consumption of the cell during the clock period based on the plurality of glitch transitions.