| CPC G06F 3/147 (2013.01) [G09G 3/2096 (2013.01); G09G 3/3688 (2013.01); G09G 2310/0272 (2013.01); G09G 2310/0291 (2013.01); G09G 2310/066 (2013.01); G09G 2310/08 (2013.01); G09G 2370/14 (2013.01)] | 5 Claims |
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1. An output driver that makes a binary input signal into differential signal and outputs the same, the output driver comprising:
a differential signaling circuit that comprises a first transistor that generates a bias current, a first node and a second node, and a resistor circuit connected between the first node and the second node, and outputs voltages generated respectively at the first node and the second node as a pair of differential signals by supplying the bias current to one of the first node and the second node based on a level of the input signal;
a differential voltage circuit that supplies a differential voltage representing a difference between a center voltage of voltages between the first node and the second node and a predetermined reference voltage to a gate of the first transistor; and
a pre-emphasis circuit that executes a pre-emphasis processing in response to changes in the level of the input signal, generating a current based on the differential voltage and adding it to the bias current,
wherein the pre-emphasis circuit executes the pre-emphasis processing while the level of the input signal changes within a predetermined cycle, and stops the pre-emphasis processing when the level of the input signal remains constant beyond the predetermined cycle.
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