US 12,254,222 B2
Accurate programming of analog memory devices of in-memory processing devices having a crossbar array structure
Manuel Le Gallo-Bourdeau, Horgen (CH); Athanasios Vasilopoulos, Zurich (CH); Benedikt Kersting, Zurich (CH); Julian Röttger Büchel, Zurich (CH); and Abu Sebastian, Adliswil (CH)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Apr. 24, 2023, as Appl. No. 18/305,466.
Claims priority of application No. 20220100941 (GR), filed on Nov. 14, 2022.
Prior Publication US 2024/0160348 A1, May 16, 2024
Int. Cl. G11C 11/00 (2006.01); G06F 3/06 (2006.01); G11C 11/56 (2006.01)
CPC G06F 3/0679 (2013.01) [G11C 11/56 (2013.01)] 25 Claims
OG exemplary drawing
 
20. A computer program product for programming memory elements of an in-memory computing device, which has a crossbar array structure including N input lines and M output lines interconnected at cross-points defining N×M cells, where N≥2 and M≥2, wherein the cross-points include respective memory systems, each including a group of K memory elements arranged in parallel, where K≥2, whereby each cell of the N×M cells includes K memory elements, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by processing means of a programming unit connectable to the in-memory computing device, to cause the programming unit to program said each cell, given a target conductance value corresponding to a target weight value to be stored in said each cell, by:
applying a SET signal to the K memory elements of said each cell to set each of the K memory elements to a SET state and reading K conductance values of the K memory elements in the SET state; and
adjusting, based on the K conductance values read and the target conductance value, a conductance value of at least one of the K memory elements to:
match a summed conductance of the K memory elements of said each cell with the target conductance value, and
maximize a number of the K memory elements that are either in their SET state or in a RESET state of zero conductance nominal value, such that at most one of the K memory elements is neither in a SET state nor in a RESET state.