| CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01)] | 19 Claims |

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1. A data storage device, comprising:
a non-volatile memory, including a plurality of dies, and a signal timing adjustment circuit, wherein the dies are grouped into storage zones; and
a controller, and a plurality of data lines coupling the controller to the non-volatile memory, wherein, through the data lines, the controller issues a plurality of commands to provide zone delay parameters to the non-volatile memory to drive the signal timing adjustment circuit to separately adjust data-line timing of the different storage zones;
wherein:
each die corresponds to multiple data lines for reading and writing; and
the commands each uses address information to specify a specific data-line number of a specific storage zone of the non-volatile memory to set read delay parameters and write delay parameters; and
the dies of the non-volatile memory are accessed through a plurality of channels, the dies sharing the same channel are activated by a plurality of chip-enable signals in an interleaved way, each chip-enable signal controls at least one die in each channel, and each die is coupled to multiple data lines which have different data-line numbers.
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