US 12,254,217 B2
Dynamic multi-bank memory command coalescing
Johnathan Alsop, Bellevue, WA (US); and Shaizeen Dilawarhusen Aga, Santa Clara, CA (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on May 2, 2023, as Appl. No. 18/311,166.
Application 18/311,166 is a continuation of application No. 16/900,526, filed on Jun. 12, 2020, granted, now 11,681,465.
Prior Publication US 2023/0266924 A1, Aug. 24, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0644 (2013.01); G06F 3/0673 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory controller comprising:
a request queue configured to store requests that target a memory; and
control circuitry configured to service a plurality of requests stored in the request queue with a single command by sending the single command to each of at least two banks of the memory, responsive to the plurality of requests in the request queue satisfying a condition.