US 12,254,215 B2
Memory device and management method thereof
Jia-Xing Lin, Hsinchu (TW); Nai-Ping Kuo, Hsinchu (TW); Shih-Chou Juan, Hsinchu (TW); Chien-Hsin Liu, Hsinchu (TW); and Shunli Cheng, Hsinchu (TW)
Assigned to MACRONIX International Co., Ltd., Hsinchu (TW)
Filed by MACRONIX International Co., Ltd., Hsinchu (TW)
Filed on Sep. 29, 2022, as Appl. No. 17/955,555.
Prior Publication US 2024/0111453 A1, Apr. 4, 2024
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a controller; and
at least one memory channel, comprising:
at least one memory chip, commonly coupled to the controller through an interrupt signal wire, wherein the at least one memory chip generate at least one local interrupt signal and performs a logic operation on the at least one local interrupt signal to generate a common interrupt signal, and the interrupt signal wire is configured to transmit the common interrupt signal to the controller,
wherein each of the local interrupt signals is configured to indicate a completion status of an operation command of each of the at least one memory chip, the logic operation is a logic AND operation, the corresponding local interrupt signal is at a logic 0 when each of the at least one memory chip has completed the operation command and is in an idle status, and the corresponding local interrupt signal is at a logic 1 when each of the at least one memory chip has not completed the operation command and is in a busy status.