US 12,254,214 B2
Input output control device
Tetsuro Takizawa, Nisshin (JP)
Assigned to DENSO CORPORATION, Kariya (JP); TOYOTA JIDOSHA KABUSHIKI KAISHA, Toyota (JP); and MIRISE Technologies Corporation, Nisshin (JP)
Filed by DENSO CORPORATION, Kariya (JP); TOYOTA JIDOSHA KABUSHIKI KAISHA, Toyota (JP); and MIRISE Technologies Corporation, Nisshin (JP)
Filed on Sep. 27, 2023, as Appl. No. 18/475,359.
Claims priority of application No. 2022-166580 (JP), filed on Oct. 18, 2022.
Prior Publication US 2024/0126474 A1, Apr. 18, 2024
Int. Cl. G06F 3/00 (2006.01); G06F 3/06 (2006.01)
CPC G06F 3/0656 (2013.01) [G06F 3/0613 (2013.01); G06F 3/0673 (2013.01)] 6 Claims
OG exemplary drawing
 
1. An input output control device connected between a verification circuit and a semiconductor memory device and controlling data input and data output, the input output control device comprising:
a first port that receives at least one read transaction for requesting reading of data in the semiconductor memory device from the verification circuit, and outputs a read response, received from the semiconductor memory device in response to the at least one read transaction, to the verification circuit;
a second port that outputs the at least one read transaction to the semiconductor memory device, and receives the read response output from the semiconductor memory device in response to the at least one read transaction;
a buffer device that delays at least one of an output of the at least one read transaction to the semiconductor memory device and an output of the read response to the verification circuit; and
a band counter device that counts an access data amount, wherein each read transaction has a corresponding size and specifies at least a data amount and an access target address, wherein the access data amount is a total of the sizes of the at least one read transaction output to the semiconductor memory device within a predefined time, wherein:
the band counter device suspends the output of the at least one read transaction to the semiconductor memory device via the second port when the access data amount exceeds a preset target band; and the band counter device outputs the at least one read transaction to the semiconductor memory device via the second port when the access data amount is equal to or smaller than the preset target band.