US 12,254,212 B2
Result register with readout counter value
Tommaso Bacigalupo, Fuerstenfeldbruck (DE); Marco Bachhuber, Neuried (DE); and Michael Krug, Munich (DE)
Assigned to Infineon Technologies AG, Neubiberg (DE)
Filed by Infineon Technologies AG, Neubiberg (DE)
Filed on May 2, 2023, as Appl. No. 18/311,052.
Prior Publication US 2024/0370197 A1, Nov. 7, 2024
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0655 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0673 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A circuit comprising:
one or more datastores configured to store a result register and a readout counter value; and
logic circuitry coupled to the one or more datastores and configured to:
cause, for a cycle of a plurality of cycles of a periodic signal, one or more analog-to-digital converters (ADCs) to store data to the result register;
modify the readout counter value in response to the one or more ADCs storing the data to the result register for the cycle; and
in response to a read request for the data at the result register for the cycle;
output the data stored by the result register;
output the readout counter value for the cycle; and
after the output of the readout counter value, set the readout counter value to a predetermined value.