| CPC G06F 3/0632 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01)] | 28 Claims |

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1. A memory initialization apparatus, comprising:
a memory controller comprising at least one second processor core; and
a first processor core configured to invoke the at least one second processor core of the memory controller to perform memory initialization,
wherein the first processor core is further configured to:
after channel initialization is completed for any memory channel, initialize, by using the any memory channel and at least one memory chip connected to the any memory channel, a component other than the memory chip.
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