US 12,254,071 B2
Semiconductor device
Satoshi Yoshimoto, Isehara (JP); Susumu Kawashima, Atsugi (JP); Koji Kusunoki, Isehara (JP); and Kazunori Watanabe, Machida (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on Aug. 24, 2023, as Appl. No. 18/237,437.
Application 18/237,437 is a continuation of application No. 17/623,294, granted, now 11,741,209, previously published as PCT/IB2020/056156, filed on Jun. 30, 2020.
Claims priority of application No. 2019-129555 (JP), filed on Jul. 11, 2019.
Prior Publication US 2024/0028680 A1, Jan. 25, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/041 (2006.01); G06F 21/32 (2013.01); G06V 40/13 (2022.01)
CPC G06F 21/32 (2013.01) [G06F 3/0412 (2013.01); G06F 3/04164 (2019.05); G06V 40/1318 (2022.01)] 13 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a light-emitting device and an imaging device,
wherein the imaging device comprises a gate driver circuit,
wherein the imaging device is configured to operate in a first mode or a second mode,
wherein the gate driver circuit comprises first to m-th register circuits for the first mode, first to p-th register circuits for the second mode, a buffer circuit, a first transistor, a second transistor, a third transistor, and a fourth transistor,
wherein the first to m-th register circuits for the first mode are connected with each other in series,
wherein the first to p-th register circuits for the second mode are connected with each other in series,
wherein a first output terminal of the first register circuit for the first mode is electrically connected to one of a source and a drain of the first transistor,
wherein a second output terminal of the first register circuit for the first mode is electrically connected to one of a source and a drain of the second transistor,
wherein a first output terminal of the first register circuit for the second mode is electrically connected to one of a source and a drain of the third transistor,
wherein a second output terminal of the first register circuit for the second mode is electrically connected to one of a source and a drain of the fourth transistor,
wherein the other of the source and the drain of the first transistor is electrically connected to the other of the source and the drain of the third transistor,
wherein the other of the source and the drain of the first transistor is electrically connected to the buffer circuit,
wherein the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the fourth transistor,
wherein the other of the source and the drain of the second transistor is electrically connected to the buffer circuit,
wherein m is an integer more than or equal to 2, and
wherein p is an integer more than or equal to 1 and less than m.