US 12,254,061 B2
Apparatuses and methods to accelerate matrix multiplication
Maciej Urbanski, Gdansk (PL); Brian J. Hickmann, Sherwood, OR (US); Michael Rotzin, Santa Clara, CA (US); Krishnakumar Nair, Santa Clara, CA (US); Andrew Yang, Cupertino, CA (US); Brian S. Morris, Santa Clara, CA (US); and Dennis Bradford, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Appl. No. 17/256,195
Filed by Intel Corporation, Santa Clara, CA (US)
PCT Filed Sep. 27, 2018, PCT No. PCT/PL2018/000091
§ 371(c)(1), (2) Date Dec. 26, 2020,
PCT Pub. No. WO2020/067908, PCT Pub. Date Apr. 2, 2020.
Prior Publication US 2021/0263993 A1, Aug. 26, 2021
Int. Cl. G06F 17/16 (2006.01); G06F 7/523 (2006.01); G06F 7/544 (2006.01)
CPC G06F 17/16 (2013.01) [G06F 7/523 (2013.01); G06F 7/5443 (2013.01); G06F 2207/3824 (2013.01)] 25 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a circuit comprising a set of fixed-point multipliers coupled to a set of shift registers coupled to a set of numeric conversion circuits coupled to a set of adders, and a maximum exponent determiner coupled to the set of shift registers and a normalization circuit to produce a resultant; and
at least one switch to change the circuit between a first mode and a second mode, wherein:
in the first mode, each fixed-point multiplier of the set of fixed-point multipliers is to multiply mantissas from a same element position of a first floating-point vector and a second floating-point vector to produce a corresponding product, shift corresponding products with the set of shift registers based on a maximum exponent of exponents for the corresponding products determined by the maximum exponent determiner to produce shifted products, perform a numeric conversion operation on the shifted products with the set of numeric conversion circuits based on sign bits from the same element position of the first floating-point vector and the second floating-point vector to produce signed representations of the shifted products, add the signed representations of the shifted products with the set of adders to produce a single product, and normalize the single product with the normalization circuit based on the maximum exponent into a single floating-point resultant, and
in the second mode, each fixed-point multiplier of the set of fixed-point multipliers is to multiply values from a same element position of a first integer vector and a second integer vector to produce a corresponding product, pass the products through the set of shift registers and the set of numeric conversion circuits to the set of adders without changing the products, add each corresponding product with the set of adders to produce a single integer resultant, and pass the single integer resultant through the normalization circuit without changing the single integer resultant.