US 12,253,968 B2
Serial bus protocol
Sergio Miguez Aparicio, Majadahonda (ES); and Benjamin Thomas Sarachi, Edinburgh (GB)
Assigned to STMicroelectronics (Research & Development) Limited, Buckinghamshire (GB)
Filed by STMicroelectronics (Research & Development) Limited, Marlow (GB)
Filed on Dec. 8, 2022, as Appl. No. 18/063,436.
Claims priority of application No. 21306804 (EP), filed on Dec. 16, 2021; and application No. 22305752 (EP), filed on May 20, 2022.
Prior Publication US 2023/0195679 A1, Jun. 22, 2023
Int. Cl. G06F 13/42 (2006.01); G06F 13/20 (2006.01)
CPC G06F 13/4291 (2013.01) [G06F 13/20 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a primary device configured to be connected to at least one secondary device via serial bus having a data wire and a clock wire, the primary device configured to:
provide a clock signal on the clock wire; and
transmit a frame comprising control bits on the serial bus, wherein a quantity of control bits transmitted on the serial bus at at least one location of the frame indicates a format of the frame.