US 12,253,959 B2
Memory protection for gather-scatter operations
Andrew Waterman, Berkeley, CA (US); and Krste Asanovic, Oakland, CA (US)
Assigned to SiFive, Inc., Santa Clara, CA (US)
Appl. No. 18/024,208
Filed by SiFive, Inc., San Mateo, CA (US)
PCT Filed Sep. 1, 2021, PCT No. PCT/US2021/048650
§ 371(c)(1), (2) Date Mar. 1, 2023,
PCT Pub. No. WO2022/051353, PCT Pub. Date Mar. 10, 2022.
Claims priority of provisional application 63/221,422, filed on Jul. 13, 2021.
Claims priority of provisional application 63/073,916, filed on Sep. 2, 2020.
Prior Publication US 2023/0305969 A1, Sep. 28, 2023
Int. Cl. G06F 12/14 (2006.01); G06F 9/30 (2018.01)
CPC G06F 12/1458 (2013.01) [G06F 9/30036 (2013.01); G06F 9/30038 (2023.08)] 15 Claims
OG exemplary drawing
 
1. An integrated circuit for executing instructions comprising:
a processor core including a pipeline configured to execute instructions, including gather-scatter memory instructions;
a memory protection circuit configured to check for memory protection violations with a protection granule; and
an index range circuit configured to:
memoize a maximum value of a tuple of indices stored in a vector register of the processor core as the tuple of indices is written to the vector register;
memoize a minimum value of the tuple of indices as the tuple of indices is written to the vector register;
determine a range of addresses for a gather-scatter memory instruction that takes the vector register as a set of indices based on a base address of a vector in memory, the memoized minimum value, and the memoized maximum value; and
check, using the memory protection circuit during a single clock cycle, whether accessing elements of the vector within the range of addresses will cause a memory protection violation.