US 12,253,948 B2
Software-defined coherent caching of pooled memory
Francesc Guim Bernat, Barcelona (ES); Karthik Kumar, Chandler, AZ (US); Alexander Bachmutsky, Sunnyvale, CA (US); Zhongyan Lu, Beijing (CN); and Thomas Willhalm, Sandhausen (DE)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Nov. 9, 2020, as Appl. No. 17/092,803.
Prior Publication US 2021/0064531 A1, Mar. 4, 2021
Int. Cl. G06F 12/08 (2016.01); G06F 12/0817 (2016.01)
CPC G06F 12/0828 (2013.01) [G06F 2212/621 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A compute platform comprising:
a central processing unit (CPU) having one or more cores on which software is executed including a plurality of software applications;
memory coupled to the CPU into which software is loaded;
hardware-based logic, either embedded on a System on a Chip (SoC) including the CPU or implemented in a discrete device coupled to the CPU;
a network interface including one or more ports configured to be coupled to a network or fabric via which disaggregated memory is accessed;
wherein execution of a portion of the software programs the hardware-based logic to implement, for each of one or more of the plurality of software applications, a software-defined caching policy to effect caching of at least a portion of an address space in the disaggregated memory allocated for the software application, and wherein data are cached in one or more disaggregated memory (DM) caches embedded on the SoC or embedded on the discrete device.