US 12,253,924 B2
Error rate measurement apparatus and error rate measurement method
Hiroyuki Onuma, Kanagawa (JP)
Assigned to ANRITSU CORPORATION, Kanagawa (JP)
Filed by ANRITSU CORPORATION, Kanagawa (JP)
Filed on May 16, 2023, as Appl. No. 18/318,283.
Claims priority of application No. 2022-125666 (JP), filed on Aug. 5, 2022.
Prior Publication US 2024/0045778 A1, Feb. 8, 2024
Int. Cl. G06F 11/22 (2006.01); G06F 11/273 (2006.01); G06F 11/32 (2006.01)
CPC G06F 11/221 (2013.01) [G06F 11/2268 (2013.01); G06F 11/2733 (2013.01); G06F 11/326 (2013.01)] 6 Claims
OG exemplary drawing
 
1. An error rate measurement apparatus that executes a matrix scan function for measuring a bit error rate by transmitting a test signal by a combination of coefficient values in a Full Swing value defined by a PCI Express standard to a device under test (W) during link training, and receiving a measurement target signal returned back from the device under test in response to transmission of the test signal, wherein
the test signal is based on a parameter value of a cell as a scanning target selected and set from a triangular matrix by the combination of the coefficient values,
three types of coefficient values are provided in the Full Swing value, and
the error rate measurement apparatus comprises:
a display control unit that displays a first coefficient value in a selectable manner by tabs of a number corresponding to the Full Swing value, uses each one of combinations of the first coefficient value, each second coefficient value, and each third coefficient value on the selected tab as the cell, displays an error count value and the bit error rate for each cell, which are obtained by the matrix scan function on a display screen in a matrix, and identifies and displays the bit error rate for each cell on the display screen, according to an error degree.