US 12,253,913 B2
Memory error tracking and logging
Farid Nemati, Los Altos Hills, CA (US); Steven R. Hutsell, San Jose, CA (US); Derek R. Kumar, Cupertino, CA (US); Bernard J. Semeria, Palo Alto, CA (US); James Vash, Los Gatos, CA (US); Era K. Nangia, Los Altos, CA (US); and Gregory S. Mathews, Saratoga, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Feb. 12, 2024, as Appl. No. 18/438,802.
Application 18/438,802 is a continuation of application No. 17/804,950, filed on Jun. 1, 2022, granted, now 11,934,265.
Claims priority of provisional application 63/267,546, filed on Feb. 4, 2022.
Prior Publication US 2024/0427663 A1, Dec. 26, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/10 (2006.01); G06F 11/07 (2006.01)
CPC G06F 11/1068 (2013.01) [G06F 11/076 (2013.01); G06F 11/0772 (2013.01); G06F 11/106 (2013.01)] 20 Claims
OG exemplary drawing
 
13. A method, comprising:
executing, by a computing system, program instructions, wherein at least some of the instructions access data in a memory;
tracking, by the computing system using multiple tracking entries, numbers of detected correctable errors associated with multiple respective locations of data accessed by one or more processors of the computing system; and
in response to detecting a threshold number of correctable errors for a particular memory location, generate a signal to at least one of the one or more processors, wherein the signal identifies the particular memory location.