US 12,253,912 B2
Memory including error correction circuit and operating method thereof
Jin Ho Jeong, Gyeonggi-do (KR); Dae Suk Kim, Gyeonggi-do (KR); and Munseon Jang, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Feb. 17, 2023, as Appl. No. 18/170,530.
Claims priority of application No. 10-2022-0156976 (KR), filed on Nov. 22, 2022.
Prior Publication US 2024/0168845 A1, May 23, 2024
Int. Cl. G06F 11/10 (2006.01); G06F 11/07 (2006.01)
CPC G06F 11/1068 (2013.01) [G06F 11/076 (2013.01); G06F 11/0772 (2013.01)] 13 Claims
OG exemplary drawing
 
1. An operating method of a memory, the operating method comprising:
reading, from selected memory cells included in the memory, codewords including data and an error correction code;
detecting errors in the codewords;
correcting the errors in the codewords;
re-writing the error-corrected codewords to the selected memory cells;
re-reading the re-written error-corrected codewords from the selected memory cells;
determining whether the errors are permanent errors in response to a determination that an error is present in the re-read error-corrected codewords;
classifying a row where a greatest number of errors are detected among rows of the memory as a first candidate of a bad region, while preferentially classifying a row including the permanent errors among rows having a same greatest number of errors as the first candidate of the bad region as a second candidate of the bad region; and
classifying the second candidate of the bad region as the bad region when the same greatest number of errors of the second candidate of the bad region is greater than or equal to a threshold value.