US 12,253,911 B2
Programmable and high-performance data scrambler for non-volatile memory controllers
Xin Guo, San Jose, CA (US); Ravi Motwani, Fremont, CA (US); Donia Sebastian, Fair Oaks, CA (US); and Aaron Lutzker, Walnut Creek, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Nov. 24, 2021, as Appl. No. 17/534,944.
Prior Publication US 2022/0083419 A1, Mar. 17, 2022
Int. Cl. G06F 11/10 (2006.01); G06F 3/06 (2006.01); G06F 7/58 (2006.01); G06F 11/07 (2006.01)
CPC G06F 11/1068 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0623 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 7/588 (2013.01); G06F 11/0772 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor apparatus comprising:
one or more substrates; and
logic coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable or fixed-functionality hardware, the logic to:
generate a first set of scrambler bits based on a destination page number associated with data;
generate a second set of scrambler bits based on a programmable nonlinear function; and
combine the first set of scrambler bits and the second set of scrambler bits into a scrambler seed, wherein the scrambler seed is a single scrambler seed.