| CPC G06F 11/0727 (2013.01) [G06F 3/0619 (2013.01); G06F 3/064 (2013.01); G06F 3/0679 (2013.01); G06F 11/073 (2013.01); G06F 11/0751 (2013.01); G06F 11/076 (2013.01); G06F 11/0793 (2013.01); G06F 11/10 (2013.01); G06F 11/1004 (2013.01); G06F 11/1008 (2013.01); G06F 11/1068 (2013.01); G06F 11/1402 (2013.01); G06F 13/4286 (2013.01); H03M 13/09 (2013.01); H03M 13/29 (2013.01); H03M 13/2906 (2013.01); H03M 13/611 (2013.01); H04L 1/0061 (2013.01); H04L 1/08 (2013.01); H04L 1/1867 (2013.01); G06F 11/1044 (2013.01); H04L 1/0003 (2013.01); H04L 1/0008 (2013.01); H04L 2001/0093 (2013.01)] | 20 Claims |

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1. A solid state memory device, comprising:
a link interface configurable in a first configuration and a second configuration, the first configuration to be for bidirectional communication with a controller via the link interface, the second configuration to be for unidirectional communication with the controller via the link interface, wherein the link interface includes:
receiver circuitry to receive command information, command error detection information associated with the command information, and remedial action instructions from the controller; and
circuitry to communicate a group of data bits with the controller based on the command information, the group of data bits to be time multiplexed with error-detection information; and,
circuitry to, based on the remedial action instructions, perform a remedial action.
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