US 12,253,876 B2
Method for programming an FPGA
Heiko Kalte, Paderborn (DE); and Dominik Lubeley, Paderborn (DE)
Assigned to dSPACE GMBH, Paderborn (DE)
Filed by dSPACE GmbH, Paderborn (DE)
Filed on Jun. 14, 2023, as Appl. No. 18/209,558.
Claims priority of application No. 10 2022 115 631.1 (DE), filed on Jun. 23, 2022.
Prior Publication US 2023/0418324 A1, Dec. 28, 2023
Int. Cl. G06F 1/10 (2006.01); G06F 11/30 (2006.01)
CPC G06F 1/10 (2013.01) [G06F 11/3051 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A method for programming an FPGA, wherein a library with elementary operations that are executable on the FPGA and a respective latency table for each of the elementary operations of the library are provided, wherein each latency table specifies, for a plurality of clock rates of the FPGA and for a plurality of input bit widths of the respective operation, the latency of the respective operation during execution on the FPGA as a function of the input bit width of the respective operation and the clock rate of the FPGA, the method comprising:
defining a data path that specifies a sequential execution on the FPGA of at least two elementary operations of the library;
recording the latencies given by the respective input bit width of the respective elementary operations of the data path for a multiplicity of clock rates that are different from one another in the latency tables;
adding the recorded latencies for every clock rate so that a total latency for the data path results in each case for this multiplicity of different clock rates;
determining a lowest total latency;
determining, for all clock rates, a ratio between a lowest total latency and a total latency at a respective clock rate;
identifying a utilization of the FPGA for each clock rate;
determining a lowest utilization of the FPGA;
determining, for all clock rates, a ratio between the lowest utilization of the FPGA and the utilization of the FPGA at a respective clock rate; and
determining a quality factor for each clock rate while taking into account the total latency and the utilization of the FPGA,
wherein the utilization of the FPGA at a specific clock rate includes the resource demand and/or the power demand on the FPGA at the clock rate in question,
wherein the resource demand or the power demand on the FPGA is identified at a specific clock rate with the aid of previously provided resource demand tables or power demand tables, and
wherein the resource demand tables or the power demand tables specify the resource demand or the power demand of a specific operation during execution on the FPGA as a function of the input bit width of the specific operation and the clock rate of the FPGA for a multiplicity of clock rates of the FPGA and for a multiplicity of input bit widths of the specific operation.