US 12,253,573 B2
Interconnect resistance compensation for cell voltage measurements under high current conditions
James Robert Pressgrove, Kokomo, IN (US); and Raghuram Devanur Chandrashekharaiah, Kokomo, IN (US)
Assigned to Green Cubes Technology, LLC, Kokomo, IN (US)
Appl. No. 18/015,122
Filed by Green Cubes Technology, LLC, Kokomo, IN (US)
PCT Filed Jun. 22, 2021, PCT No. PCT/US2021/038351
§ 371(c)(1), (2) Date Jan. 9, 2023,
PCT Pub. No. WO2022/010639, PCT Pub. Date Jan. 13, 2022.
Claims priority of provisional application 63/050,229, filed on Jul. 20, 2020.
Prior Publication US 2023/0258736 A1, Aug. 17, 2023
Int. Cl. G01R 31/396 (2019.01); G01R 31/385 (2019.01); G01R 31/389 (2019.01); G01R 35/00 (2006.01)
CPC G01R 31/396 (2019.01) [G01R 31/3865 (2019.01); G01R 31/389 (2019.01); G01R 35/005 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of compensating for interconnect resistance between a plurality of electrically coupled cells of a battery:
providing a computer having a processor in communication with a storage medium, the storage medium having instructions stored thereon and accessible by the processor, wherein the instructions comprise an algorithm configured to calculate voltage loss measurements due to interconnect resistance between the plurality of electrically coupled cells in the battery, wherein the algorithm performs the steps of:
calculating the interconnect resistance between the plurality of electrically coupled cells of the battery during an initial battery design phase;
wherein the interconnect resistance is a calibration value; and
programming the calibration value into a BMS of the battery at manufacture to optimize battery performance.