| CPC G01R 31/3177 (2013.01) [G01R 31/31725 (2013.01)] | 16 Claims |
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1. An electronic device, comprising:
a functional circuit, disposed within the electronic device and coupled to at least one signal port that is to be connected to an external device externally coupled to the electronic device, for performing at least one functional operation in response to at least one control signal sent from the external device;
a test mode circuit, coupled to the functional circuit, for controlling the functional circuit performing at least one test operation in response to a test pattern signal sent from a verification circuit; and
the verification circuit, disposed within the electronic device and coupled to the test mode circuit, for performing an on-chip test and verification operation upon the function circuit by converting the test pattern signal into a plurality of test waveform signals based on a clock signal provided from the test mode circuit, generating and outputting the plurality of test waveform signals into the test mode circuit, receiving a plurality of test result waveform signals from the test mode circuit when the at least one test operation corresponding to the test pattern signal is performed, converting a target pattern signal into a plurality of target result waveform signals, and then comparing the plurality of test result waveform signals with the plurality of target result waveform signals to determine and output a failure result signal into the test mode circuit, the failure result signal being used to indicate whether at least one failure occurs;
wherein the electronic device is a flash memory controller chip circuit; and, the verification circuit comprises:
a memory circuit, arranged for storing the test pattern signal and the target pattern signal;
a counter circuit, arranged for counting and outputting a counting value into a comparator circuit in response to a signal edge of the clock signal;
the comparator circuit, coupled to the counter circuit, for generating and outputting a trigger signal as an enable signal into a plurality of test comparison circuits respectively when the counting value is equal to a specific value; and
the plurality of test comparison circuits, arranged for receiving a plurality of test bits of the test pattern signal to perform a serial-to-parallel conversion upon the plurality of test bits to output the plurality of test waveform signals into the test mode circuit through a plurality of input/output nodes respectively, receiving the plurality of test result waveform signals from the test mode circuit respectively through the plurality of input/output nodes, receiving a plurality of target result bits of the target pattern signal to perform the serial-to-parallel conversion upon the plurality of target result bits to generate the plurality of target result waveform signals to respectively compare the plurality of target result waveform signals with the plurality of test result waveform signals to generate a plurality of fail information bit signals so as to form and output the failure result signal.
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