US 12,253,558 B2
Circuit test structure and method of using
Ching-Fang Chen, Hsinchu (TW); Hsiang-Tai Lu, Hsinchu (TW); and Chih-Hsien Lin, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Nov. 22, 2023, as Appl. No. 18/517,260.
Application 14/700,822 is a division of application No. 13/356,243, filed on Jan. 23, 2012, granted, now 9,040,986, issued on May 26, 2015.
Application 18/517,260 is a continuation of application No. 17/229,269, filed on Apr. 13, 2021, granted, now 11,828,790.
Application 17/229,269 is a continuation of application No. 16/401,850, filed on May 2, 2019, granted, now 11,002,788, issued on May 11, 2021.
Application 16/401,850 is a continuation of application No. 15/633,136, filed on Jun. 26, 2017, granted, now 10,288,676, issued on May 14, 2019.
Application 15/633,136 is a continuation of application No. 14/700,822, filed on Apr. 30, 2015, granted, now 9,689,914, issued on Jun. 27, 2017.
Prior Publication US 2024/0094282 A1, Mar. 21, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/00 (2006.01); G01R 31/28 (2006.01); H01L 21/66 (2006.01); H01L 23/12 (2006.01); H01L 23/498 (2006.01)
CPC G01R 31/2856 (2013.01) [G01R 31/2886 (2013.01); H01L 22/34 (2013.01); H01L 23/12 (2013.01); H01L 23/49827 (2013.01); H01L 24/16 (2013.01); H01L 2224/13099 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/16227 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A circuit test structure comprising:
a chip including a conductive line which traces a perimeter of the chip;
an interposer electrically connected to the chip, wherein the conductive line is over both the chip and the interposer;
a test structure connected to the conductive line; and
a testing site, wherein the test structure is configured to electrically connect the testing site to the conductive line.