US 11,930,721 B2
Systems and methods for fabrication of superconducting integrated circuits
Eric Ladizinsky, Manhattan Beach, CA (US); Jeremy P. Hilton, Burnaby (CA); Byong Hyop Oh, San Jose, CA (US); and Paul I. Bunyk, New Westminster (CA)
Assigned to 1372934 B.C. LTD., Burnaby (CA)
Filed by D-WAVE SYSTEMS INC., Burnaby (CA)
Filed on May 8, 2020, as Appl. No. 16/870,537.
Application 15/679,963 is a division of application No. 14/383,837, granted, now 9,768,371, issued on Sep. 19, 2017, previously published as PCT/US2013/029680, filed on Mar. 7, 2013.
Application 16/870,537 is a continuation of application No. 15/679,963, filed on Aug. 17, 2017, granted, now 10,700,256.
Claims priority of provisional application 61/608,379, filed on Mar. 8, 2012.
Claims priority of provisional application 61/714,642, filed on Oct. 16, 2012.
Prior Publication US 2020/0274050 A1, Aug. 27, 2020
This patent is subject to a terminal disclaimer.
Int. Cl. H10N 60/01 (2023.01); B82Y 10/00 (2011.01); H01L 21/285 (2006.01); H01L 21/768 (2006.01); H10N 60/10 (2023.01); H10N 60/12 (2023.01); H10N 60/80 (2023.01); H10N 60/85 (2023.01); H10N 69/00 (2023.01); G06N 10/00 (2022.01)
CPC H10N 60/0912 (2023.02) [B82Y 10/00 (2013.01); H01L 21/2855 (2013.01); H01L 21/76877 (2013.01); H01L 21/76891 (2013.01); H10N 60/01 (2023.02); H10N 60/0156 (2023.02); H10N 60/10 (2023.02); H10N 60/12 (2023.02); H10N 60/805 (2023.02); H10N 60/855 (2023.02); H10N 69/00 (2023.02); G06N 10/00 (2019.01)] 12 Claims
OG exemplary drawing
 
1. A method of fabricating a superconducting integrated circuit, the method comprising:
depositing a first dielectric layer;
depositing a negative photoresist mask over the first dielectric layer that traces out a negative pattern of a desired circuit pattern such that the desired circuit pattern corresponds to regions of the first dielectric layer that are not directly covered by the negative photoresist mask;
etching the desired circuit pattern into the first dielectric layer to produce open features in the first dielectric layer;
depositing a first superconducting metal layer over the first dielectric layer to at least partially fill the open features in the first dielectric layer;
planarizing the first superconducting metal layer;
depositing a second dielectric layer to produce a desired inner layer dielectric thickness, wherein the inner layer dielectric thickness is controlled by a deposition process; and
depositing a second superconducting metal layer above the second dielectric layer.